On 29/11/2019 12:09, Jan Beulich wrote: > On 25.11.2019 18:22, Roger Pau Monne wrote: >> When using global pages a full tlb flush can only be performed by >> toggling the PGE bit in CR4, which is usually quite expensive in terms >> of performance when running virtualized. This is specially relevant on >> AMD hardware, which doesn't have the ability to do selective CR4 >> trapping, but can also be relevant on Intel if the underlying >> hypervisor also traps on accesses to the PGE CR4 bit. >> >> In order to avoid this performance penalty, do not use global pages >> when running in shim mode. Note this is done when running on both >> Intel or AMD hardware, since older versions of Xen capable of running >> the shim don't make use of Intel selective CR4 trapping feature and >> will vmexit on every access to CR4. > So here you say you do this uniformly because of older Xen. > What about newer Xen? Is this still a win (or at least not a > loss) there? Independent of underlying hardware? In case of > any kind of doubt I think this would want to be command line > controllable.
Older Xen has VMExits for all CR4.PGE flips. Newer Xen (since 4.10? iirc) on Intel hardware (with HAP) arranged for CR4.PGE flips not to vmexit. There is no ability to cause CR4.PGE flips to not vmexit on AMD, other than to give the guest full control of CR4 which is a BadThing(tm). I agree that this wants a command line control, but it wants to be enabled by default any time we find ourselves nested on AMD hardware, not just in shim. ~Andrew _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
