On 25.11.2019 18:22, Roger Pau Monne wrote: > When using global pages a full tlb flush can only be performed by > toggling the PGE bit in CR4, which is usually quite expensive in terms > of performance when running virtualized. This is specially relevant on > AMD hardware, which doesn't have the ability to do selective CR4 > trapping, but can also be relevant on Intel if the underlying > hypervisor also traps on accesses to the PGE CR4 bit. > > In order to avoid this performance penalty, do not use global pages > when running in shim mode. Note this is done when running on both > Intel or AMD hardware, since older versions of Xen capable of running > the shim don't make use of Intel selective CR4 trapping feature and > will vmexit on every access to CR4.
So here you say you do this uniformly because of older Xen. What about newer Xen? Is this still a win (or at least not a loss) there? Independent of underlying hardware? In case of any kind of doubt I think this would want to be command line controllable. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
