> -----Original Message----- > From: Oleksandr <olekst...@gmail.com> > Sent: 25 September 2019 16:50 > To: Paul Durrant <paul.durr...@citrix.com>; 'Jan Beulich' <jbeul...@suse.com> > Cc: Petre Pircalabu <ppircal...@bitdefender.com>; Stefano Stabellini > <sstabell...@kernel.org>; Wei Liu > <w...@xen.org>; KonradRzeszutek Wilk <konrad.w...@oracle.com>; Andrew Cooper > <andrew.coop...@citrix.com>; David Scott <d...@recoil.org>; Tim (Xen.org) > <t...@xen.org>; George Dunlap > <george.dun...@citrix.com>; Tamas K Lengyel <ta...@tklengyel.com>; Ian Jackson > <ian.jack...@citrix.com>; Anthony Perard <anthony.per...@citrix.com>; > xen-devel@lists.xenproject.org; > Volodymyr Babchuk <volodymyr_babc...@epam.com>; Roger Pau Monne > <roger....@citrix.com>; Julien Grall > <julien.gr...@arm.com> > Subject: Re: [Xen-devel] [PATCH v13 0/4] add per-domain IOMMU control > > > [CC Julien] > > > Hi Paul > > I may mistake, but looks like > > 80ff3d338dc93260b41ffeeebb0f852c2edef9ce iommu: tidy up > iommu_use_hap_pt() and need_iommu_pt_sync() macros > > triggers ASSERT_UNREACHABLE on Arm if no IOMMU has been found (I built > with my platform's IOMMU driver disabled: # CONFIG_IPMMU_VMSA is not set) .
Oh, I'm sure I was told this was not a possibility for ARM, which is why iommu_hap_pt_share ended up being #defined. Seems I was misled, in which case ARM ought to be have a more dynamic config. as with x86. Paul > > So, iommu_setup() calls clear_iommu_hap_pt_share() with > iommu_hap_pt_share being set (CONFIG_IOMMU_FORCE_PT_SHARE=y) which, > actually, triggers ASSERT. > > ... > > > (XEN) Assertion 'unreachable' failed at > ...ild-workspace/build/xen/xen/include/xen/iommu.h:72 > (XEN) ----[ Xen-4.13-unstable arm64 debug=y Not tainted ]---- > (XEN) CPU: 0 > (XEN) PC: 00000000002b3ae0 iommu_setup+0xa0/0x18c > (XEN) LR: 00000000002b3a8c > (XEN) SP: 00000000002f7dc0 > (XEN) CPSR: a0000249 MODE:64-bit EL2h (Hypervisor, handler) > (XEN) X0: 00000000002a7000 X1: 0000000000000000 X2: 2c736173656e6572 > (XEN) X3: 0000000000000002 X4: 0000000000000001 X5: 0000000000000000 > (XEN) X6: 0000000000000080 X7: 2b726072646d6471 X8: 7f7f7f7f7f7f7f7f > (XEN) X9: ff65685e6c6f7275 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 > (XEN) X12: 0000000000000038 X13: 0000000000280910 X14: 0000000000000020 > (XEN) X15: 0000000000000000 X16: 00000000002a7000 X17: 00000000002a7000 > (XEN) X18: 00000000002a7000 X19: 0000000000000000 X20: 00000000ffffffed > (XEN) X21: 00000000002a6380 X22: 0000000000335430 X23: 0000000000000002 > (XEN) X24: 000000000029b1f0 X25: 00000000002d83d0 X26: 0000000048000000 > (XEN) X27: 00000000c0000000 X28: 0000000000000001 FP: 00000000002f7dc0 > (XEN) > (XEN) VTCR_EL2: 80000000 > (XEN) VTTBR_EL2: 0000000000000000 > (XEN) > (XEN) SCTLR_EL2: 30cd183d > (XEN) HCR_EL2: 0000000000000038 > (XEN) TTBR0_EL2: 00000000781b4000 > (XEN) > (XEN) ESR_EL2: f2000001 > (XEN) HPFAR_EL2: 0000000000000000 > (XEN) FAR_EL2: 0000000000000000 > (XEN) > (XEN) Xen stack trace from sp=00000000002f7dc0: > (XEN) 00000000002f7de0 00000000002bdd94 0000000000000002 0000000000000002 > (XEN) 00000000bfe0b660 00000000002001b4 0000000078080000 0000000077e80000 > (XEN) 0000000048000000 0000000000000000 0000000000400000 0000000000000003 > (XEN) 0000000000000001 0000000000000000 0000000078080000 0000000048080040 > (XEN) 0000000000000000 000000000000f080 0000000048000000 0000000078000000 > (XEN) 00000000002d83c0 00000000002aa440 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000300000000 0000000000000000 00000040ffffffff > (XEN) 0000000000000400 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > (XEN) Xen call trace: > (XEN) [<00000000002b3ae0>] iommu_setup+0xa0/0x18c (PC) > (XEN) [<00000000002b3a8c>] iommu_setup+0x4c/0x18c (LR) > (XEN) [<00000000002bdd94>] start_xen+0xaa0/0xc7c > (XEN) [<00000000002001b4>] arm64/head.o#primary_switched+0xc/0x2c > (XEN) > (XEN) > (XEN) **************************************** > (XEN) Panic on CPU 0: > (XEN) Assertion 'unreachable' failed at > ...ild-workspace/build/xen/xen/include/xen/iommu.h:72 > (XEN) **************************************** > (XEN) > > > -- > Regards, > > Oleksandr Tyshchenko _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
