On 14.03.2024 15:45, Andrew Cooper wrote: > On 13/03/2024 5:27 pm, Andrew Cooper wrote: >> Start cleaning it up with ffs() and friends. Across the board, this adds: >> >> * Functioning bitops without arch-specific asm > > It turns out that RISC-V doesn't have a CLZ instruction in the base > ISA. As a consequence, __builtin_ffs() emits a library call to ffs() on > GCC, or a de Bruijn sequence on Clang. > > The optional Zbb extension adds a CLZ instruction, after which > __builtin_ffs() emits a very simple sequence. > > This leaves us with several options. > > 1) Put generic_ffs() back in, although if we do this then it's going to > be out-of-line in lib/ where it can be mostly ignored. > > 2) Require Zbb for Xen. > > 3) Alternative it up with Zbb or generic_ffs(). > > > I've got half a mind to do 1) irrespective. It's mostly just shuffling > logic out of bitops.h into lib/.
Yes. Might also help with the bi-sectability issue you faced. > I also think we should do option 2 for RISCV. Given the instruction > groups that H does mandate, it's unrealistic to expect that such a chip > wouldn't support Zbb/etc. I'm not so sure here. > Also, getting full alternatives working is yet-more work that's not > trivial at this point in RISCV's development. I think it is entirely > reasonable to avoid this work for now, and make it a problem for anyone > who has an H-capable Zbb-incapable system. (with a strong implication > that this is work that probably never needs to be done.) That's definitely for later. Jan
