On 18.10.2023 10:54, Roger Pau Monné wrote: > On Wed, Oct 18, 2023 at 09:54:15AM +0200, Jan Beulich wrote: >> Taking together perhaps: >> - nr_pt_levels needs setting to the larger of 3 and 4, depending on what >> hardware supports, for use in non-pass-through entries, >> - a new max_pt_levels field needs setting to what would result from your >> code change above, for use in pass-through entries, > > It needs to be a per-IOMMU field, as I would assume IOMMUs can have > different page table level support on the same system?
Right, hence why I also said "field". >> - min_pt_levels could then remain as is, >> - for the moment we ignore the forward-compatibility aspect, until the >> underlying principle has been clarified by Intel. >> >> A possible further complication then is that we will end up switching >> context entries between different AW values. That's not an issue when >> we use CMPXCHG16B or transiently clear the present bit, but our best >> effort fallback would likely be of security concern then. > > We would need to update the AW context entry field unconditionally in > domain_context_mapping_one(). Plus (just so it's not missed) purge the corresponding assertion. > Hm, it's likely more change than what I was expecting to perform at > this point in the release, but I guess we cannot ignore the fact that > SAGAW might now have bit 3 set and hence passthrough mode is broken on > such systems. Ideally yes. Of course for the immediate purpose we might go with the smaller change, but then with the description mentioning (and justifying) the omission. If there are 5-level IOMMUs in the wild, I'm afraid that wouldn't be a (good) option though. Otoh people shouldn't be using hwdom-pass-through mode in the first place ... Jan
