On 05/06/2023 4:54 pm, Jan Beulich wrote:
> On 05.06.2023 17:10, Roger Pau Monne wrote:
>> As specified on Errata 1474:
>>
>> "A core will fail to exit CC6 after about 1044 days after the last
>> system reset. The time of failure may vary depending on the spread
>> spectrum and REFCLK frequency."
>>
>> Detect when running on AMD Fam17h models 30h-3fh and setup a timer to
>> prevent entering C6 after 1000 days have elapsed. Take into account
>> the TSC value at boot in order to account for any time elapsed before
>> Xen has been booted.
> Models 6x are also affected as per their RG. I have some trouble with
> the site, so it's too slow going to actually try and fish out the RGs
> for the other possible models.
>
> Given more than one set of models is affected I of course also wonder
> whether Hygon CPUs wouldn't be affected, too. But I realize we have
> hardly any means to find out.
I'd say it's more likely than unlikely, and ...
>> @@ -1189,3 +1190,44 @@ const struct cpu_dev amd_cpu_dev = {
>> .c_early_init = early_init_amd,
>> .c_init = init_amd,
>> };
>> +
>> +static void cf_check disable_c6(void *arg)
>> +{
>> + printk(XENLOG_WARNING
>> + "Disabling C6 after 1000 days uptime due to AMD errata 1474\n");
>> + amd_disable_c6 = true;
>> +}
>> +
>> +static int __init cf_check amd_c6_errata(void)
>> +{
>> + /*
>> + * Errata #1474: A Core May Hang After About 1044 Days
>> + * Set up a timer to disable C6 after 1000 days uptime.
>> + */
>> + s_time_t;
>> +
>> + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
>> + boot_cpu_data.x86 != 0x17 ||
>> + (boot_cpu_data.x86_model & 0xf0) != 0x30)
> Perhaps better ... & ~0xf, just to be future-proof?
... this wants to follow the same logic as for Branch Type Confusion.
See amd_init_spectral_chicken() looking for STIBP.
It's very likely all Zen2 models, given that it will have taken nearly 3
years to be discovered in the first place...
~Andrew
