On 05/06/2023 4:10 pm, Roger Pau Monne wrote:
> diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
> index 0d3143031b5b..728fa61a54bb 100644
> --- a/xen/arch/x86/cpu/amd.c
> +++ b/xen/arch/x86/cpu/amd.c
> @@ -1189,3 +1190,44 @@ const struct cpu_dev amd_cpu_dev = {
> .c_early_init = early_init_amd,
> .c_init = init_amd,
> };
> +
> +static void cf_check disable_c6(void *arg)
> +{
> + printk(XENLOG_WARNING
> + "Disabling C6 after 1000 days uptime due to AMD errata 1474\n");
> + amd_disable_c6 = true;
I don't think this is good enough.
AMD CPUs can enter C6 from HLT and IOCstate as well as via MWAIT.
You're going to need to modify the MSRs as described in the revision
guide, which will inhibit all ways of entering C6.
~Andrew
