Hi Michal, > -----Original Message----- > Subject: [PATCH 2/3] xen/arm: vpl011: Handle correctly TXFE when backend in > Xen > > When backend is in Xen, the handling of data written to DR register is a > bit special because we want to tell guest that we are always ready for new > data to be written (i.e. no real FIFO, TXFF/BUSY never set and TXI always > set). This conflicts with the current handling of TXFE bit, which we > always clear and never set on a write path (we happen to set it when we > receive char from serial input due to use of vpl011_data_avail() but this > might never be called). This can lead to issues if a guest driver makes > use of TXFE bit to check for TX transmission completion (such guest could > then wait endlessly). Fix it by keeping TXFE always set to match the > current emulation logic. > > Signed-off-by: Michal Orzel <michal.or...@amd.com>
Reviewed-by: Henry Wang <henry.w...@arm.com> Tested-by: Henry Wang <henry.w...@arm.com> Kind regards, Henry
