On 20.01.2023 15:59, Oleksii Kurochko wrote:
> +/* On stack VCPU state */
> +struct cpu_user_regs
> +{
> + register_t zero;
> + register_t ra;
> + register_t sp;
> + register_t gp;
> + register_t tp;
> + register_t t0;
> + register_t t1;
> + register_t t2;
> + register_t s0;
> + register_t s1;
> + register_t a0;
> + register_t a1;
> + register_t a2;
> + register_t a3;
> + register_t a4;
> + register_t a5;
> + register_t a6;
> + register_t a7;
> + register_t s2;
> + register_t s3;
> + register_t s4;
> + register_t s5;
> + register_t s6;
> + register_t s7;
> + register_t s8;
> + register_t s9;
> + register_t s10;
> + register_t s11;
> + register_t t3;
> + register_t t4;
> + register_t t5;
> + register_t t6;
> + register_t sepc;
> + register_t sstatus;
> + /* pointer to previous stack_cpu_regs */
> + register_t pregs;
> +};
What is the planned correlation of this to what x86 a Arm have in their
public headers (under the same name)? I think the public header want
spelling out first, and if a different internal structure is intended to
be used, the interaction between the two would then want outlining in
the description here.
Jan
