The patch introduces a set of registers which should be saved to and
restored from a stack after an exception occurs and a set of defines
which will be used during exception context saving/restoring.
Originally <asm/processor.h> header was introduced in the patch series
from Bobby so mostly it was re-used and removed unneeded things from
it now.
Signed-off-by: Bobby Eshleman <bobby.eshle...@gmail.com>
Signed-off-by: Oleksii Kurochko <oleksii.kuroc...@gmail.com>
---
xen/arch/riscv/include/asm/processor.h | 114 +++++++++++++++++++++++++
1 file changed, 114 insertions(+)
create mode 100644 xen/arch/riscv/include/asm/processor.h
diff --git a/xen/arch/riscv/include/asm/processor.h
b/xen/arch/riscv/include/asm/processor.h
new file mode 100644
index 0000000000..5898a09ce6
--- /dev/null
+++ b/xen/arch/riscv/include/asm/processor.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: MIT */
+/******************************************************************************
+ *
+ * Copyright 2019 (C) Alistair Francis <alistair.fran...@wdc.com>
+ * Copyright 2021 (C) Bobby Eshleman <bobby.eshle...@gmail.com>
+ * Copyright 2023 (C) Vates
+ *
+ */
+
+#ifndef _ASM_RISCV_PROCESSOR_H
+#define _ASM_RISCV_PROCESSOR_H
+
+#include <asm/types.h>
+
+#define RISCV_CPU_USER_REGS_zero 0
+#define RISCV_CPU_USER_REGS_ra 1
+#define RISCV_CPU_USER_REGS_sp 2
+#define RISCV_CPU_USER_REGS_gp 3
+#define RISCV_CPU_USER_REGS_tp 4
+#define RISCV_CPU_USER_REGS_t0 5
+#define RISCV_CPU_USER_REGS_t1 6
+#define RISCV_CPU_USER_REGS_t2 7
+#define RISCV_CPU_USER_REGS_s0 8
+#define RISCV_CPU_USER_REGS_s1 9
+#define RISCV_CPU_USER_REGS_a0 10
+#define RISCV_CPU_USER_REGS_a1 11
+#define RISCV_CPU_USER_REGS_a2 12
+#define RISCV_CPU_USER_REGS_a3 13
+#define RISCV_CPU_USER_REGS_a4 14
+#define RISCV_CPU_USER_REGS_a5 15
+#define RISCV_CPU_USER_REGS_a6 16
+#define RISCV_CPU_USER_REGS_a7 17
+#define RISCV_CPU_USER_REGS_s2 18
+#define RISCV_CPU_USER_REGS_s3 19
+#define RISCV_CPU_USER_REGS_s4 20
+#define RISCV_CPU_USER_REGS_s5 21
+#define RISCV_CPU_USER_REGS_s6 22
+#define RISCV_CPU_USER_REGS_s7 23
+#define RISCV_CPU_USER_REGS_s8 24
+#define RISCV_CPU_USER_REGS_s9 25
+#define RISCV_CPU_USER_REGS_s10 26
+#define RISCV_CPU_USER_REGS_s11 27
+#define RISCV_CPU_USER_REGS_t3 28
+#define RISCV_CPU_USER_REGS_t4 29
+#define RISCV_CPU_USER_REGS_t5 30
+#define RISCV_CPU_USER_REGS_t6 31
+#define RISCV_CPU_USER_REGS_sepc 32
+#define RISCV_CPU_USER_REGS_sstatus 33
+#define RISCV_CPU_USER_REGS_pregs 34
+#define RISCV_CPU_USER_REGS_last 35
+
+#define RISCV_CPU_USER_REGS_OFFSET(x) ((RISCV_CPU_USER_REGS_##x) *
__SIZEOF_POINTER__)
+#define RISCV_CPU_USER_REGS_SIZE RISCV_CPU_USER_REGS_OFFSET(last)
+
+#ifndef __ASSEMBLY__
+
+/* On stack VCPU state */
+struct cpu_user_regs
+{
+ register_t zero;
+ register_t ra;
+ register_t sp;
+ register_t gp;
+ register_t tp;
+ register_t t0;
+ register_t t1;
+ register_t t2;
+ register_t s0;
+ register_t s1;
+ register_t a0;
+ register_t a1;
+ register_t a2;
+ register_t a3;
+ register_t a4;
+ register_t a5;
+ register_t a6;
+ register_t a7;
+ register_t s2;
+ register_t s3;
+ register_t s4;
+ register_t s5;
+ register_t s6;
+ register_t s7;
+ register_t s8;
+ register_t s9;
+ register_t s10;
+ register_t s11;
+ register_t t3;
+ register_t t4;
+ register_t t5;
+ register_t t6;
+ register_t sepc;
+ register_t sstatus;
+ /* pointer to previous stack_cpu_regs */
+ register_t pregs;
+};
+
+static inline void wait_for_interrupt(void)
+{
+ __asm__ __volatile__ ("wfi");
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_PROCESSOR_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.39.0
