v->arch.vmpidr is assigned to uint64_t variable. This is to enable left shifts
for Aarch32 so that one can extract affinity bits.
This is then assigned to 'typer' so that the affinity bits form the upper 32
bits.
Refer Arm IHI 0069H ID020922,
The upper 32 bits of GICR_TYPER represent the affinity
whereas the lower 32 bits represent the other bits (eg processor
number, etc).
Signed-off-by: Ayan Kumar Halder <ayank...@amd.com>
---
Changes from :-
1. v1 - Assigned v->arch.vmpidr to "uint64_t vmpdir". Then, we can use
MPIDR_AFFINITY_LEVEL macros to extract the affinity value.
xen/arch/arm/vgic-v3.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 3f4509dcd3..e5e6f2c573 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -191,13 +191,15 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v,
mmio_info_t *info,
case VREG64(GICR_TYPER):
{
uint64_t typer, aff;
+ uint64_t vmpidr = v->arch.vmpidr;
if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
- aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 |
- MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 |
- MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 |
- MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32);
+ aff = (MPIDR_AFFINITY_LEVEL(vmpidr, 3) << 56 |
+ MPIDR_AFFINITY_LEVEL(vmpidr, 2) << 48 |
+ MPIDR_AFFINITY_LEVEL(vmpidr, 1) << 40 |
+ MPIDR_AFFINITY_LEVEL(vmpidr, 0) << 32);
typer = aff;
+
/* We use the VCPU ID as the redistributor ID in bits[23:8] */
typer |= v->vcpu_id << GICR_TYPER_PROC_NUM_SHIFT;
--
2.17.1
