> >>> On 15.01.18 at 19:12, <luwei.k...@intel.com> wrote: > > Luwei Kang (7): > > x86: add a flag to enable Intel processor trace > > x86: configure vmcs for Intel processor trace virtualization > > x86: add intel proecessor trace support for cpuid > > x86: add intel processor trace context > > x86: Implement Intel Processor Trace context switch > > x86: Implement Intel Processor Trace MSRs read/write > > x86: Disable Intel Processor Trace when VMXON in L1 guest > > How can this be a re-send of v1 when the original v1 consisted of just 6 > patches? >
Yes, I make some change in Intel PT context switch(only save /load guest state when Intel PT is enabled in guest), Intel PT MSRs pass through strategy (only passthrough MSRs when PT is enabled in guest) and add a patch (patch 7) to disable Intel PT-VMX in nested. Because of there just have some high level comments from community and above all changes is from my point of view. So I re-send this patch set still as v1. Thanks, Luwei Kang _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
