> >>> On 12.12.16 at 07:51, <luwei.k...@intel.com> wrote:
> > By the way, I think another place may need to do some modify as well.
> >
> > @@ -868,7 +868,7 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs
> > *regs)
> > if ( is_pmc_quirk )
> > handle_pmc_quirk(msr_content);
> > core2_vpmu_cxt->global_status |= msr_content;
> > - msr_content = ~global_ovf_ctrl_mask;
> > + msr_content &= ~global_ovf_ctrl_mask;
> > wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
> > }
> >
> > If one counter have overflow all the bit will be clean. I think it
> > need add & with current status.
> >
> > Hi jan and Andrew,
> > What is your opinion?
>
> I agree, but it looks to be an independent change.
>
Hi Jan,
Thanks for your reply. I will submit another patch regarding " msr_content
&= ~global_ovf_ctrl_mask;" soon.
What is your opinion about this patch? Need any modify?
Thanks,
Luwei Kang
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