> - The serial controller on the Tegra SoCs doesn't behave in the same > was as most NS16550-compatibles; it actually adheres to the NS16550 > spec a little more rigidly than most compatible controllers. A > coworker (Chris Patterson, cc'd) figured out what was going on; from > what I understand, most 16550s generate the "transmit ready" interrupt > once, when the device first can accept new FIFO entries. Both the > original 16550 and the Tegra implementation generate the "transmit > ready" interrupt /continuously/ when there's space available in the > FIFO, slewing the CPU with a stream of constant interrupts.
That may also be an issue on x86 I would think. Is there some simple 16550 'fix' for this? As in reprogram it to not be soo ready? _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
