On Wed, 2015-11-18 at 17:27 +0000, Julien Grall wrote: > Each ITARGETSR register are 4-byte wide and the offset is in byte.
"is 4-bytes" ... "is in bytes". > > The current implementation is computing the offset of ICFGR1 and ICFG2 > wonrgly result to emulate only the first 2 byte of the ICFGR<n> range wrongly > read-only. The rest will be treated as read-write. > > For convenience introduce ITARGETSR1 and ITARGETSR2. > > Signed-off-by: Julien Grall <julien.gr...@citrix.com> > --- > > We only store the value of ICFGR<n> registers for the guest own > purpose > today. Xen is not using it at all. So I don't think it's worth to > backport > it. > > Changes in v2: > - This patch was supposed to be in v1, but messed up the > git format-patch command > --- > xen/arch/arm/vgic-v2.c | 6 ++++-- > xen/include/asm-arm/gic.h | 2 ++ > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c > index c94f0f3..4fb954b 100644 > --- a/xen/arch/arm/vgic-v2.c > +++ b/xen/arch/arm/vgic-v2.c > @@ -507,10 +507,12 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, > mmio_info_t *info, > > case GICD_ICFGR: /* SGIs */ > goto write_ignore_32; > - case GICD_ICFGR + 1: /* PPIs */ > + > + case GICD_ICFGR1: This should have a /* PPIs */ comment I think? I think I could add that on commit if you agree. Ian. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
