On 13/08/15 10:20, Jan Beulich wrote: >> BTW, IIRC x86 does modify at least one ACPI table which is the DMAR (I >> think), to hide the IOMMU from the guest? That's another table we would >> want to frob on ARM I think (or it's equivalent, which I think is IORT). > > Eliminating that hack is supposed to be on the VT-d maintainers' > TODO list(s) - Dom0 has no business looking at that table (and its > AMD counterpart already isn't being fiddled with in the same way).
ARM SMMU is supporting 2 stage in order to protect the device also by the domain. At some point we will expose it to DOM0 and therefore may need to modify IORT. Regards, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
