>>> On 24.07.15 at 14:11, <roger....@citrix.com> wrote:
> El 24/07/15 a les 12.46, Jan Beulich ha escrit:
>>>>> On 24.07.15 at 11:59, <roger....@citrix.com> wrote:
>>>     __DECL_GP_REG(flags);
>> 
>> r8-r11, selector and descriptor registers, pseudo descriptor registers.
>> Or else for all of them their default state would need to be spelled out.
> 
> r8-r15 right?

Oh - of course.

>>>     /* Control registers.         */
>>>     uint64_t cr[8];
>>>     /* Valid on amd64 only.       */
>> 
>> Fields valid/useful in one mode only should probably be put in
>> union-ized sub-structures.
> 
> Do you mean something like:
> 
>     union {
>         uint64_t efer;
>         uint32_t __invalid32;
>         uint16_t __invalid16;
>     }
> 
> It seems kind of pointless IMHO, the reason to have the union is to be
> able to access the registers using the native nomenclature, but if a
> register doesn't exist in a specific bitness I don't see the point of
> adding such "invalid" names.

No - put side by side an item valid in only a subset modes and an
item only valid outside of that subset.

> Or your idea was to put all the bitness specific registers inside of
> another separate structure and then unionize them? AFAICT the 16 and
> 32bit structures are going to be empty.

How that? 64-bit mode e.g. doesn't need full descriptor data for
many of the segment registers.

Jan


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