>>> On 28.11.14 at 04:28, <liang.z...@intel.com> wrote:
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -4287,7 +4287,7 @@ void hvm_cpuid(unsigned int input, unsigned int *eax,
> unsigned int *ebx,
> !host_tsc_is_safe() )
> *edx &= ~cpufeat_mask(X86_FEATURE_RDTSCP);
> /* Hide 1GB-superpage feature if we can't emulate it. */
> - if (!hvm_pse1gb_supported(d))
> + if (!hvm_pse1gb_supported(d) || paging_mode_shadow(d))
> *edx &= ~cpufeat_mask(X86_FEATURE_PAGE1GB);
With
#define hvm_pse1gb_supported(d) \
(cpu_has_page1gb && paging_mode_hap(d))
the change above is pointless. While, considering this, comments on
v2 may have been misleading, you should have simply updated the
patch description instead to clarify why the v2 change was okay
even for the shadow mode case.
Jan
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