On Fri, Aug 15, 2025 at 12:25 AM Wade Fife <[email protected]> wrote:
> Brian, > > Are you enabling pause frames? It is required when transmitting to the > USRP at high rates with 100 GbE. > > https://files.ettus.com/manual/page_transport.html#transport_udp_linux > > Unfortunately, as far as I know, it's not yet enabled by default for some > technical reasons. So be sure to turn it on after each FPGA reload or > reboot. > We actually can't use pause frames/flow control in this application. I am fine with dropped frames as a result of this, but I need the link to still be robust to lots of traffic. I was surprised to see the pings stop since that's a CPU path, and not a CHDR path from the ethernet transport adapter. > > You should be able to read those registers by doing raw memory read/writes > to the system bus. The register offsets are here: > > > https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/rfnoc/xport_sv/eth_regs.vh > > The base address for QSFP0 I think is 0x12_0000_8000, so REG_CHDR_DROPPED, > for example, should be at 0x12_0000_9030. The base address for QSFP1 should > be 0x12_0001_8000. > > For example, running this should return the bottom part of the MAC address: > > devmem2 0x1200009010 > Excellent - this is what I was looking for with the registers! I'll try this out today. > > Hopefully I've got the details right. I'm traveling at the moment, so I > can't easily verify. > Good luck traveling. I'll update this thread when I figure out more today. Brian
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