Wade, Thank you for this, I took a look at repeat_fpga_build.py and I think that will be very helpful. I am going to add some modifications that log the types of failures I get and the amount.
I have the issue with two different builds, both with two custom RFNoC blocks and HLS modules for my logic. I am building an x310 image, and both of these builds have completed before with the same HLS verilog files used. One thing that is worth mentioning is I get a timing violation in a pulse stretcher module from UHD. However, when I have gotten that error the build generates the bit file and it still works for my use case on the FPGA. That has been around for some time and I don't think it is the cause of this recent issue. I will try and get the stats from the repeat_fpga_build.py and reply in the coming days. Thanks, David On Thu, Mar 6, 2025 at 9:01 AM Wade Fife <wade.f...@ettus.com> wrote: > Hi David, > > I'm surprised that you're seeing it that frequently. The Ettus continuous > integration tests build FPGAs regularly and from what I understand this > issue is pretty rare there. This makes me wonder if there's something about > the images you're building that causes this to reproduce more frequently > for you. Can you estimate what percentage of unique builds (with a unique > build seed or git hash) fail? Which FPGA image are you building? Does it > have custom logic in it? > > You could use the repeat_fpga_build.py script to automate building the > FPGA multiple times to get a successful build. It automates the process of > selecting a unique seed for each build and can even run multiple build jobs > at a time. > > Thanks, > > Wade > > On Mon, Mar 3, 2025 at 1:30 PM David <vitishlsfa...@gmail.com> wrote: > >> Using UHD 4.6/Ubuntu 22.04/x310, I have built many images in the last >> year or so with rfnoc_image_builder. Recently in the last month, I get the >> following error on almost all images: >> >> [image: image.png] >> >> I have tried the following, after referencing this the known issues >> section in the USRP3 build instructions ( >> https://files.ettus.com/manual/md_usrp3_build_instructions.html): >> >> 1. doing the suggested and making a non-functional source code >> change and recommitting the git >> 2. deleting the .git directory in both the block directory and the >> uhd/ directory where the fpga build happens >> 3. changing the build seed in uhd/fpga/usrp3/top/x300/Makefile >> 4. Running on a different machine, copying the block source code and >> using a different UHD git all together (private rehost vs the github UHD). >> The vivado 2021.1 install is the same as its on a network file system >> >> These do not produce repeatable good results. Maybe once a week or once >> every two weeks one of these things will finish the build. This has been >> happening for about a month or two, and I don't know how else to >> troubleshoot. >> >> Any advice? >> >> Thanks, >> >> David >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> >
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