Hi, thanks for the reply. I’m using UHD 4.7. I ran the following and it worked
fine:\
\
$ source ../setupenv.sh --vivado-path=/opt/tools/Xilinx/Vivado/
Setting up a 64-bit FPGA build environment for the USRP-X4xx...
\- Vivado: Found (/opt/tools/Xilinx/Vivado//2021.1/bin)
Installed version is Vivado v2021.1_AR76780 (64-bit)
Environment successfully initialized.\
\
However, from there, I ran rfsoc_image_builder:\
\
\
$ rfnoc_image_builder -y x410_CG_400_rfnoc_image_core.yml -t x410_CG_400
--vivado-path /opt/tools/Xilinx/Vivado/
Using FPGA directory /home/computer/uhd/fpga
Selected device: x410
Launching build with the following settings:
\* FPGA Directory: /home/computer/uhd/fpga/usrp3/top/x400
\* Build Artifacts Directory:
/home/computer/uhd/fpga/usrp3/top/x400/build-usrp_x410_fpga_CG_400
\* Build Output Directory: /home/computer/uhd/fpga/usrp3/top/x400/build
\* Build IP Directory: /home/computer/uhd/fpga/usrp3/top/x400/build-ip
Executing the following command: /bin/bash -c ". ./setupenv.sh
--vivado-path=/opt/tools/Xilinx/Vivado/ && make x410_CG_400
BUILD_DIR=/home/computer/uhd/fpga/usrp3/top/x400/build-usrp_x410_fpga_CG_400
IMAGE_CORE_NAME=usrp_x410_fpga_CG_400"
Setting up a 64-bit FPGA build environment for the USRP-X4xx...
\- Vivado: Found (/opt/tools/Xilinx/Vivado//2021.1/bin)
Installed version is Vivado v2021.1_AR76780 (64-bit)
Environment successfully initialized.
make: \*\*\* No rule to make target 'x410_CG_400'. Stop.\
\
I’m guessing its supposed to make the .bit file but not able to. I also tried
running the Makefile.inc in the build folder (make -f Makefile.inc)\
$ make -f Makefile.inc
make: \*\*\* No targets. Stop.\
\
This is what it looks like:\
LIB_DIR := $(HOME)/uhd/fpga/usrp3/lib
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/hwutils/Makefile.srcs
include $(LIB_DIR)/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/Makefile.srcs
include $(LIB_DIR)/rfnoc/transport_adapters/rfnoc_ta_chdr_dma/Makefile.srcs
RFNOC_XDC_SRCS = \\
constraints/pins/qsfp0_0.xdc \\
constraints/pins/qsfp0_1.xdc \\
constraints/pins/qsfp0_2.xdc \\
constraints/pins/qsfp0_3.xdc \\
constraints/pins/qsfp1_0.xdc \\
constraints/pins/qsfp1_1.xdc \\
constraints/pins/qsfp1_2.xdc \\
constraints/pins/qsfp1_3.xdc \\
RFNOC_IMAGE_CORE_SRCS += $(abspath \\
$(BUILD_DIR)/rfnoc_image_core.sv \\
$(RFNOC_CORE_HEADERS) \\
$(RFNOC_BLOCK_RADIO_SRCS) \\
$(HWUTILS_SRCS) \\
$(RFNOC_TA_X4XX_ETH_SRCS) \\
$(RFNOC_TA_CHDR_DMA_SRCS) \\
)
RFNOC_IMAGE_CORE_DEFS = RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
DRAM_W=64 QSFP0_0=5 QSFP0_1=0 QSFP0_2=0 QSFP0_3=0 QSFP1_0=5 QSFP1_1=0 QSFP1_2=0
QSFP1_3=0\
\
\
Any idea what the issue is?
_______________________________________________
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-le...@lists.ettus.com
