Martin, Thanks for letting me know. I can add in and proceed.
For a YAML creation wizard, it would benefit my typical use case. I will give a little background and have my suggestions at the bottom. I work on images with either SISO or MISO processing, where the output is some math processing such as a linear combination of channels. My flow to setup such a block in UHD 4.6 after running rfnocmodtool new/add is: 1. change all fpga interfaces to axis_pyld_ctxt to axis_data 2. change the context_fifo_depth to info_fifo_depth 3. add whatever number of channels I need, OR add the number of ports on a single input 4. run create_verilog I admit that those steps are fairly trivial, but having an easy option in the new tool to generate multiple I/O (or NUM_PORTS), and choose their fpga interface would be nice. I prefer using the axis_data interface because it exposes the sideband channels. In all my cases, I pass through the sidebands except the axis_thas_time (=1'b0). This lets my DUC/TX block transmit as soon as possible without me worrying about time commands. Whether or not that is the correct method, disabling timestamp output in the yaml would be a cool option for me. In summary my suggestions would be 1. add the create_verilog functionality directly into the new rfnoc_modtool 2. automatic yaml creation, be able to change the fpga interfaces between the 3 listed in the RFNoC spec 3. variable number of inputs and outputs, potentially named with list of string options 4. be able to disable timestamps with any of the interfaces (I use axis_data specifically for this since it is very simple) 5. adding a custom clock and setting the interface clock domain (like user0 in the RFNoC spec example on page 81) A lot of these options are listed and explained in detail in the RFNoC spec, and these suggestions are purely a quality of life change that would save me 15 minutes when I make a block. Thanks, David On Wed, Jan 29, 2025 at 2:27 AM Martin Braun <martin.br...@ettus.com> wrote: > Hi David, > > and sorry for stumbling over the lack of documentation for this (fairly > new) tool. Yes, the idea is that you create the YAML. rfnoc_modtool add > will then generate the HDL, noc_shell, block controller templates, etc. > > We've been internally discussing a kind of YAML creation wizard -- would > that be of interest to you? What should it do in your opinion? > > --M > > On Tue, Jan 28, 2025 at 10:13 PM David <vitishlsfa...@gmail.com> wrote: > >> Hello, >> >> All my experience in UHD is in UHD4.6. I am trying out UHD 4.8 because of >> the upgrades to rfnoc_image_builder, and I tried making a test module with >> rfnoc_modtool. >> >> Running "rfnoc_modtool create test_module" completes successfully, >> however running "rfnoc_modtool add test_block" generates the following >> error: >> >> [image: image.png] >> >> The test_block.yml indeed doesn't exist, and I am wondering if the >> intention is that I add it myself, or if the creation of the file was >> accidentally omitted. >> >> I enabled debug during the module creation, and can see how it >> copies/edits files from share and renames them, but I don't see the yaml >> created and it doesn't exist in <install dir>/share/uhd/rfnoc-newmod/ >> >> Thanks, >> >> David >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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