On 08/01/2025 01:47, frie...@free.fr wrote:
My understanding is that the clock signal fed to the daughter-cards
is typically some fraction of the master_clock
frequency, and is designed to provide a REF signal for
synthesizers, etc. It should be synchronized to the
ADC clocks, but won't necessarily be at the same frequency.
I have further investigated and I see
1/ a clear clock signal between GND and clk_p (J38 pin 2
on https://files.ettus.com/schematics/basic_dbs/BasicRX.pdf)
of the BasicRX board for about 1-s when the USRP Source Block in
GNU Radio Companion displays
[INFO] [X300] Radio 1x clock: 200 MHz
but then the signal vanishes
2/ I can change this short clock signal frequency by providing the
argument dboard_clock_rate to the USRP Source Block: I have checked
that the default frequency is 100 MHz, I can request 50 MHz and RFNOC
somewhat complains when requesting 200 MHz but still the clock signal
is visible for a second.
so this signal can be controlled from software. Is there a way to keep
the signal as the flowgraph is running rather than only a second or so
at startup?
Thanks
My guess is that the basic_rx host-side driver turns it off, because the
basic_rx doesn't actually use it, so it would be floating, and
thus potentially radiating and causing an issue at both the
fundamental and odd harmonics.
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