Hi, we've been making a lot of improvements to the RFNoC tooling recently, so if you can, I recommend you update as much as you can (if you can, go to HEAD of master branch, if not, at least go the latest release). Note that rfnoc-example is now called rfnoc-gain. We've been testing this build for X310 and X410 quite a bit, so that should do the trick.
--M On Thu, Dec 19, 2024 at 11:55 AM <elkana...@gmail.com> wrote: > Hello, > > I'm new to RFNoC and have been trying to implement the example described > in "Getting Started with RFNoC in UHD 4.0." Unfortunately, all my attempts > have failed. Here's what I've done so far: > > $ cp -r <repo>/host/examples/rfnoc-example ~/ > $ mv ~/rfnoc-example ~/rfnoc-demo > $ mkdir ~/rfnoc-demo/build > $ cd ~/rfnoc-demo/build > $ cmake -DUHD_FPGA_DIR=<repo>/fpga/ ../ > $ make > $ make install > $ make x310_rfnoc_image_core > > However, I encountered an error right at the beginning of the process, > which seems to be related to the clocks. I've tried modifying gain.yml > and x310_rfnoc_image_core.yml files, but nothing has worked. > > I am using UHD 4.6, and I couldn't find any updated documentation for this > version. Here's a summary of the errors I face: > > 1. > > *If I run the command without changing file parameters:* > > ERROR: [Synth 8-448] named port connection 'gtrefclk' does not exist for > instance 'core_support_i' of module 'one_gig_eth_pcs_pma_support' > ERROR: [Synth 8-448] named port connection 'gtrefclk_bufg' does not exist > for instance 'core_support_i' of module 'one_gig_eth_pcs_pma_support' > ERROR: [Synth 8-6156] failed synthesizing module 'one_gige_phy' > ERROR: [Synth 8-6156] failed synthesizing module 'x300_sfpp_io_core' > ERROR: [Synth 8-6156] failed synthesizing module 'x300' > ERROR: [Common 17-69] ... > > 2. > > *If I change clk_domains and add:* > > codesrcblk: _device_, srcport: ce, dstblk: gain0, dstport: ce > > I get: > > [ERR] 1 Unresolved clk domain(s) > [ERR] (_device_-> gain0-ce) > [ERR] Source or destination domain not found > > 3. > > *If I change the clk_domains from ce to rfnoc_chdr:* > > ERROR: [synth 8-1031] gain0_rfnoc_chdr_clk is not declared > [../../x310_rfnoc_image_core.v:1216] > ERROR: [Common 17-69] Command failed ... > > > I’ve also tried other configurations, but none seem to work. > Interestingly, I can build images for RFNoC blocks (FFT, FIR, etc.), but > not for out-of-tree (OOT) blocks. > > Any guidance or advice would be greatly appreciated. > > Thank you! > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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