Hey Mark, maybe I'm being dense, but I don't understand what it is that your GPIO pins are supposed to be doing when your system is done. Can you elaborate?
--M On Wed, Nov 6, 2024 at 1:56 AM <mgan...@gmail.com> wrote: > Hi everybody! > > I’ve written an RFNOC block that assigns the daughterboard rx GPIO pins to > the tdata signals that are sent to the SEP. I’m using the axis_data > protocol and the block is placed statically between the DDC and the SEP. I > use the tvalid and tlast signal from the upstream (DDC) block and the > tready signal from the downstream (SEP) block. I brought the GPIO into the > block using appropriate YAML files. Small modification outside of RFNOC > were required to get the pins to RFNOC (bus_int.v, x300_core.v, > io_signatures.yml, and x310_bsp.yml). > > The x310 is operated at 1 Msps and there are 64 samples per CHDR packet on > the axis data bus. This means that the packet rate on the bus is 1 Msps / > 64, or 15.625 kHz. Period is 64 us. > > If I place a signal onto the GPIO pin, everything is fine as long as the > pulse width is greater than 64 us. I can run the radio with > rx_samples_to_file and see the GPIO pins faithfully reproduced in the > Ethernet output collected on a PC. > > At pulse widths less than 64 us, the signal is essentially aliased. I > believe it’s because I’m using the tvalid, tlast, and tready signals from > upstream/downstream blocks with data that’s already on the axis data plane. > That data bursts through with 64 samples roughly every 64 us and is clocked > with a 200 MHz master clock. I need to clock in the asynchronous GPIO. > > My question: What is the best way to do this? Generate my own clock and > use a generic FIFO like axi_fifo.v to hold the data until the upstream > block sends its data and the downstream block is ready to receive? > > Thank you, > > Mark > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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