Hello together, hi build UHD version 4.6 on the fft_cp_preview2 branch, I don’t know if this is (already) supported. And With the YAML files there I build the FPGA Image (x410_x4_200_fft_ddc_duc_rfnoc_image_core.yml) just at it was an flashed it to the USRP. All of this just worked fine. I Also can Use the fft blocks with the cyclic prefix.
Just two questions came up to me while tinkering with the ofdm_loopback.py example script. As far as I understand using the -l flag I avoid using the analog frontend and with the -d flag set to for instance 50 I can set a digital delay. All this also works… Now the question if I use the analog frontend (not setting these flags) and attaching cables the delay I measure is way longer. I’ve seen there is a delay of 188 samples set between the Tx and the Rx in the example script, is this due to the FPGA setup? Is there a way to make the Rx and Tx in time-sync? I’ve seen a timed command is used there and the delays between Tx and Rx are constant, but constantly to big. I can correct for this time error, is the the following correction right 188 / tick_rate? Or is there more to compensate for?\ I tried to set the same time_offset in the transmit_and_receive function but still seen the same delay, so I guess that is a delay which can’t be removed? The other thing I have noticed is that if I set channels just to 0, away from the default which is 0,1 I don’t receive any samples. Seems like the flow graph hangs after sending, this happens regardless of using the loopback (-l) or not.. \ \ Other than that I realy like this feature in UHD and am looking forward to the official release, great work keep it up!
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