Hi Nidhi, X300 and X310 work the same way. In your YAML, put back some of the things you commented out. You need at least one SEP that has the control flag set to true. I recommend just removing the DDCs/DUCs and keeping the radios, then add your FFT block.
--M On Mon, Oct 14, 2024 at 9:42 AM Nidhi Panda <nidhi.pa...@cyronics.com> wrote: > Hello, > > I am having USRP X300 device with following tool versions: > > Vivado 2021.1 - AR76780n, > GNU radio version - v3.11.0.0git-820-g2adbd4ea > UHD version - UHD_4.7.0.0-84-gbdada1ed > > I have created an FPGA image file for HG mode using "rfnoc_image_builder". > It includes radio0/1, DDC0/1, DUC0/1 and a replay module by default. I > tested it on hardware also. It works fine. Now I want to add different > RFNoC block in my design. On following > *"https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0%22 > <https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0%22>"* guide, > I am trying to add FFT IP. This gives a multi-driven clock error in > implementation. Is it because this guide is for the X310 board? Can anyone > guide me the process of editing ".yml script "to add an FFT block for USRP > X300. I have attached my .yml script for reference. > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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