On 19/09/2024 12:02, cyberphox wrote:
Thank you and I look forward to hearing back from you & your colleagues.
So according to one of the FPGA folks on the "inside", there should be
ZERO difference
between the x300_reset.py and simply doing a power-cycle.
The reset script simply sends a special message to the ZPU, which
immediately forces a *hard* reset on
the FPGA--which will cause it to reset itself, and load the running
FPGA image from the EEPROM. This is
exactly what happens at power-up.
On Thu, 19 Sept 2024 at 15:38, Marcus D. Leech
<patchvonbr...@gmail.com> wrote:
On 19/09/2024 09:44, cyberp...@gmail.com wrote:
>
> Hi all,
>
> I am using this the x300_reset.py script to reset the FPGA and
would
> like to know a bit more about what is it resetting etc.
>
(https://github.com/EttusResearch/uhd/blob/UHD-4.0/host/utils/x300_reset.py)
>
> Power off and on does not seem to get as clean result as when I
issue
> this reset.
>
> thanks,
>
> Marino
>
>
There's not a lot of info on this utility, and it isn't officially
supported, although we've recommended its use in the past.
Most of the R&D crew at Ettus/NI/Emerson are at the Gnu Radio
conference
this week, but I've reached out to someone
in our support org who might know.
>
>
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