Hi,
I have setup an application that is constantly reading a Tx FIFO and sending burst transmissions with a SPP of S samples per packet. I want to modify my incoming signals in my RFNoC block, but I am having a hard time understanding how the samples will enter my RFNoC block through the AXI data wires. Will the tlast be asserted after S samples or will it be asserted after the entire burst is completed?
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
