Hi, regarding FPGA Rx buffer, I am wondering if you can use the DRAM as a buffer (e.g., host_tx => dram => duc => radio_tx). As far as I remember, you can't use the DRAM as a FIFO if you are running 2 channels both at 200 MS/s. The DRAM FIFO bandwidth is insufficient. But, if your data rate is less or you only have 1 Tx channel, this may be an option. I'm not positive it will solve the underrun but the DRAM FIFO is 1GB deep. This could be an alternative to using DPDK. Rob
On Mon, Jul 22, 2024 at 9:31 AM <cjohn...@serranosystems.com> wrote: > Hi, > > Thanks for the answer in 2). > > What about 1) *FPGA Rx Buffer Size:* > > - > > What is the FPGA Rx buffer size on the X310? > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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