Hi All, I have a clone of UHD 4.7 (Tags: v4.7.0.0) and am trying to build the default X310_XG FPGA to check if my setup is OK.
I ran the following commands from /uhd/fpga/usrp3/top/x300 source ./setupenv.sh rfnoc_image_builder -y x310_XG_rfnoc_image_core.yml -t X310_XG After some time I get this error: BUILDER: Adding IP: /home/gssltest/git/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_fft/axi_fft.xci BUILDER: Adding IP: /home/gssltest/git/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci ERROR: [Common 17-107] Cannot change read-only property 'generate_synth_checkpoint'. Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties. INFO: [Common 17-206] Exiting Vivado at Fri Jul 19 12:38:28 2024... Thanks for your help Marino
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