On Thu, Feb 22, 2024 at 3:02 PM <ygurupra...@umass.edu> wrote: > CRITICAL WARNING: [Route 35-39] The design did not meet timing > requirements. Please run report_timing_summary for detailed reports. > > [01:09:55] Current task: Routing +++ Current Phase: 22 Post Router Timing > > [01:09:55] Current task: Routing +++ Current Phase: Finished > > [01:09:55] Executing Tcl: phys_opt_design -directive Explore > > [01:09:55] Starting Physical Synthesis Command > > [01:10:32] Current task: Physical Synthesis +++ Current Phase: Starting > > [01:10:32] Starting Physical Synthesis Task > > [01:10:32] Current task: Physical Synthesis +++ Current Phase: Starting > > [01:12:11] Current task: Physical Synthesis +++ Current Phase: 1 Physical > Synthesis Initialization > > CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL > u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock > period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2 > u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2 > has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL > REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property. >
It looks like a precision issue in Vivado. You can safely ignore this warning. Brian
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
