I'm currently new to X310 , I have loaded the hardware with the example
(Getting started with RfNoc document),
still having few errors , even though the bit stream is generated
(Currently using vivado 2019.1 with UHD 4.2).
When I tried to add the FFT block , as per the document I got few timing
errors , unable to resolve that issue (but the bit stream was generated and
the FPGA contained the FFT block)
Similarly I wanted to add a keep 1 in n block in the RX section
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to
validate this file
copyright: >- # Copyright information used in
file headers
Ettus Research, A National Instruments Brand
license: >- # License information used in file
headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for
this image
device: 'x310'
default_target: 'X310_HG'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 65536 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size: 0
ep2:
ctrl: False
data: True
buff_size: 65536
ep3:
ctrl: False
data: True
buff_size: 0
ep4:
ctrl: False
data: True
buff_size: 4096
ep5:
ctrl: False
data: True
buff_size: 4096
ep6:
ctrl: False
data: True
buff_size: 32768
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
duc0: # NoC block name
block_desc: 'duc.yml' # Block device descriptor file
parameters:
NUM_PORTS: 1
ddc0:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
duc1:
block_desc: 'duc.yml'
parameters:
NUM_PORTS: 1
ddc1:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 2
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 64
MEM_ADDR_W: 30
keep1:
block_desc: 'keep_one_in_n.yml'
parameters:
NUM_PORTS: 1
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the
following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A TX
- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
# RF A RX
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A RX2
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B TX
- { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
# RF B RX
- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B RX2
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
#
# Keep-1-in-N Connections
- { srcblk: ep6, srcport: out0, dstblk: keep1, dstport: in_0 }
- { srcblk: keep1, srcport: out_0, dstblk: ep6, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport:
ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport:
ctrlport_radio1 }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram
}
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio
}
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio
}
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time
}
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time
}
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the
following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
- { srcblk: _device_, srcport: ce, dstblk: keep1, dstport: ce }
This is my modified yml file, is there something I need to work on the
vivado end to fix these issues??
Thanks
Yash
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