On 29/01/2024 12:20, Arnaldo Sans wrote:
Hello Marcus,
Thank you for your quick response... I am attaching a pdf of the email
because I suspect that my screenshots are not making -it to you.
Here are the TX and RX graphs available on the Ettus URL I mentioned
in my initial email...
Below are the RX plots:
1. Receiver performance – Gain, IQ Balance, DC Offset, Input IP3,
Input IP2 and Noise Figure) with a swept Gain range from 0 dB to
37.5 dB, at a fixed frequency, 5800 MHz
2. Receiver performance – (Gain, IQ Balance, DC Offset, Input IP3,
Input IP2 and Noise Figure) with a swept frequency range from 10
MHz to 6 GHz with a fixed Gain of 0.00 dB.
Below are the TX plots:
1. Receiver performance – Gain, IQ Balance, DC Offset, Output IP3,
Output IP2 and Noise Figure) with a swept Gain range from 0 dB to
37.5 dB, at a fixed frequency, 5800 MHz
2. Receiver performance – (Gain, IQ Balance, DC Offset, Output IP3,
Output IP2 and Noise Figure) with a swept frequency range from 10
MHz to 6 GHz with a fixed Gain of 0.00 dB.
I would like to know the input power, Pin?
Regarding the attenuators, below is a screenshot from the Ettus URL.
I would like to know more about what appear to be fixed attenuators
and how they are used and managed. According to the data sheet I
think I understand how the variable attenuator is being used and
managed; if there is any documentation that provides additional
details that would be very much appreciated.
*It is my understanding that the HMC624LP4E is a 6-bits, 0.5 dB steps
digital step attenuator. This means I can control as much as 31.5 dB
gain in 0.5dB steps yet the measurements show gain values up to 37.5
dB. Where are the extra 6 dB of gain control coming from?*
Regarding the request for a theory of operation documentation… this is
because currently I am only looking at block diagrams and schematics –
often time many questions can be answered by a theory of operation
document. I there another URL that has the documents?
Thank you, I appreciate you help.
Regards,
AJ
------------------------------------------------------------------------
*From:* Marcus Müller <marcus.muel...@ettus.com>
*Sent:* Monday, January 29, 2024 10:11 AM
*To:* usrp-users@lists.ettus.com <usrp-users@lists.ettus.com>
*Subject:* [USRP-users] Re: x310 USRP -- Performance questions
*Note: This message originated from outside the FIU Faculty/Staff
email system.*
Hi Arnaldo,
On 29.01.24 14:23, Arnaldo Sans wrote:
Are there any details about what the measurement conditions were
used to accomplished both the Rx and Tx measurements... e.g. input
power etc.?
Which measurements specifically are you referring to? For most of the
RX figures, input power is the actual measured quantity, of sorts?
Regarding the block diagram... I see various attenuators... that I
would like to better understand I have placed green boxes around
the attenuators
So, what would you like to understand about these attenuators?
Is there a theory of operations document / URL for the x310?
I think you're mostly looking at it; could you specify that question a
bit, please?
Best regards,
Marcus
There's no "structured walk-through" of the various hardware designs.
The schematics and the block-diagrams and the
FPGA source code, and the host-side source code, and the API
documentation, and the growing collection of app-notes
are what there is.
I'm also not sure how the "37.5dB" was obtained in testing, and TBH, the
person who did these tests is, AFAIR, long-gone
from the Emerson/NI/Ettus world.
The small fixed attenuators are likely there to buffer against
reflections from filters that follow, and/or to assure that
the max Pout cannot exceed some regulatory limit even with the
variable attenuator turned up to maximum.
The UBX is a two-stage (again, AFAIR) superheterodyne design, with the
2nd conversion stage being direct-conversion,
which is what is sampled by the ADCs on the motherboard. I believe
that converse is true for the TX side. But since
my main application for my own applications is radio astronomy, I
only rarely "care" about the TX side of things.
On TX, signals start out as quadrature baseband signals, and if they are
between 500MHz and 6GHz, the sum gets
presented directly to the RFPA output stage. If under 500MHz,
there's a 2nd conversion stage before being
presented to the RPGA output stage.
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