Hello,
There appears to be a bug related to alignment of the PPS to samples. The
issue applies to both TX and RX and was replicated on N321 and X310 using UDH
3.15 and 4.6. It therefore appears to be an FPGA issue.
TX experiment
----------------------------
* USRP is provided with external PPS and 10 MHz
* The PPS input is split and goes to the USRP and a scope
* The USRP output goes to a scope
* USRP outputs a file
*
First 1000 samples are 1, remaining are zero
* File size = sample rate (i.e. repeats every second)
* Setup the experiment using both:
* GR file_source + usrp_sink
* Sync to unknown PPS
* usrp.set_start_time(5)
* Standalone C++ application (based on tx_samples_from_file)
* Added code to set_time_unknown_pps(0), then set start time using
metadata to 5
Results:
* The USRP output is delayed relative to the PPS as observed on the scope
* The delay is ~1.2 us for X310 and ~100us for N321
* The delay changes slightly (<1us) depending on the sample rate (e.g. 10
Msps vs 20 Msps)
RX experiment
----------------------------
* USRP is provided with external PPS and 10 MHz
*
USRP input is a pulse (generated using technique above) that repeats every
second
*
Pulse is aligned to PPS, verified using a scope
*
USRP records samples starting on a second boundary (time_t(5))
*
GR usrp_source + file_sink
*
standalone C++ application (based on rx_samples_to_file)
* Added code to set_time_unknown_pps(0), then set start time using
metadata to 5
*
Recorded samples are analyzed to find the first 'large' value
Results
* Recording appears to start late relative to PPS (only verified on N321,
delay is ~100 us, same as for the TX delay)
Thoughts
* I recall (years ago) there was a fix to a similar problem. The FPGA was
modified to trigger ADC/DAC samples after the DDC rather than before. Did it
regress at some point?
* The delays are very consistent, indicating that the PPS is in fact being
used (i.e. it is not random).
* We ran some experiments to analyze the stability and accuracy of relative
timing between RX and TX (i.e. turn-around) when the start time for TX and RX
are specified. The results are excellent – delay is stable and accurate to <
100 ps.
This seems like a simple thing to fix in the FPGA – there is no reason for the
delay to be > 1 sample clock.
Eugene.
________________________
Eugene Grayver, Ph.D.
Aerospace Corp., Principal Engineer
Tel: 310.336.1274
________________________
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