Hi there, we are interested in using the USRPs (X300) to experiment with a transmission system with feedback and we want to minimize the delay from the USRP to the air. We want to understand the delays in the processing. (We will not be injecting samples through the PC but we are planning to program directly the USRP FPGA).
My understanding is that there is one source of delay in the DUC/half-band filtering in the motherboard. How much is this delay? (delay of halfband filters?) Another source of delay is inside the ADC chip that also contains filters. Is that correct? (I was looking at the Analog Devices chip for the ADC and I saw halfband filters there as well). How much is this delay? Finally there is some delay in the analog front end (SBX). Is there an estimate for this as well? thanks Achilleas
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