Hi Jeyakumar,
obviously, we'd point you to the same resources on the Ettus knowledge base that you've
already read, probably. So, um, can you maybe phrase this in a less open-ended way? What
do you need help with?
Also: "Add AI capabilities", that makes my "underdefined term usage" meter have very high
readings. Please try to also narrow down what you want this to mean!
Best,
Marcus
On 19.09.23 09:37, Jeyakumar K-[BL.EN.P2VLD22009] via USRP-users wrote:
Dear all,
Do we have any videos or can someone help me with a code walk through of USRP github
codebase.
I have taken this project as my final year MTech project and would like to add AI
capabilities after understanding the code.
Many thanks for your support.
Thanks
Jeyakumar K
------------------------------------------------------------------------------------------
*From:* Jeyakumar K-[BL.EN.P2VLD22009] <bl.en.p2vld22...@bl.students.amrita.edu>
*Sent:* 12 September 2023 11:25
*To:* usrp-users@lists.ettus.com <usrp-users@lists.ettus.com>
*Subject:* Re: Help to build and push bitstream to FPGA of USRP codebase
Can someone please help here.
Thanks
Jeyakumar
------------------------------------------------------------------------------------------
*From:* Jeyakumar K-[BL.EN.P2VLD22009]
*Sent:* 05 September 2023 21:37
*To:* usrp-users@lists.ettus.com <usrp-users@lists.ettus.com>
*Subject:* Help to build and push bitstream to FPGA of USRP codebase
Dear Users,
I tried my best following the instructions provided in build manual but the build failed
with several attempts.
As part of my final year major project, I have expressed interest to work on ettus fpga
open source git reporsitory for USRP hardware build on FPA and add more features.
Hence can anyone guide me to understand source code at high level and how to build them
in vivado. I really appreciate all your support !
Thanks
Jeyakumar
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