On Fri, Aug 4, 2023 at 3:52 AM <patrice.paju...@imt-atlantique.fr> wrote:
> Dear all, > > I plan to use 2 USPRs to analyze LTE signal. One will use a GPSDO to have > a good clock and time reference. To have synchronization between them, the > second one will be set on external synchronization (ref out -> ref in, for > 10 MHz and PPS). A Master clock of 184 is recommended for LTE. According to > previous answers of this post, this configuration is impossible. If the > second USRP can be locked on 9.96 MHz, the received frequency will be > wrong. In practice (We have just tried), the synchronization fails “Error: > RuntimeError: Reference Clock PLL failed to lock to external source”. Any > idea of a backup plan ? > If you're just doing analysis on a commodity computer, then just make sure your subcarrier spacing is set to 15 kHz with an appropriate sized FFT. FFTW can do arbitrary sized FFTs, so I'd set everything to 200 Msps and get down to a reasonable level in the FPGA using the DDC. Then on the host, I'd resample to whatever an integer multiple of that sample rate was that gave me a good FFT size. For example, 200 Msps -> 50 Msps (FPGA DDC) -> 3/5 Resampling on host -> 30 Msps -> FFT @ 2000 -> 15 kHz subcarriers. If you actually need 30.72 Msps or 61.44 Msps, then resample either in the FPGA (RFNoC block) or on the host. If you want to get into the PLL on the device, then you can see if you can program the reference input of the LMK04816 to accept a clock that isn't 10 MHz and is something else. Lots of options, but they all require some work on your part. Brian
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