Hi everyone, I am trying to understand how the system performs the samples buffering, especially in the Rx side. When you say “all the buffering is done by the socket buffers” you are talking about he **host’s** UDP socket, right ? The “socket I/O” that you are talking about is in the USRP side ? When you say “the socket I/O is synchronous”, does it mean that there is no buffering at all in the FPGA and all the samples of the USRP are constantly being pushed to the host even when I am not calling the “recv” function ?
I’m sorry of those are questions with obvious answers. I’m asking this because I performed some tests similar to those performed by Rob : I call recv(), I sleep some time and call recv() again. I saw that even when I sleep several minutes with a sample rate of 4Msps i still have no buffer overflow. Thank you very much for your support. David Fernandes
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