Hi, Any luck here? Even when specifying the mac (no arp required), the FPGA still doesn’t send anything, though the control plane believes it is.
Here is the log, but no stream being transmitted. --- > ``` > cjohnson@demo:~/ettus_repo/uhd/host/examples/python$ ./remote_rx.py > --rate=200e6 --freq=1223e6 --gain=20 --dest-addr=192.168.30.30 > --dest-port=54321 --adapter='sfp1' --dest-mac-addr=3c:ec:ef:c2:43:47 > [INFO] [UHD] linux; GNU C++ version 11.3.0; Boost_107400; > UHD_4.4.0.cjohnson-fb-sdrx-68-g02558b69 > [TRACE] [MULTI_USRP] multi_usrp::make with args Empty Device Address > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 192.168.0.255 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 192.168.30.255 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 192.168.30.255 49600 > [TRACE] [UDP] Creating udp transport for 192.168.0.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.30.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.30.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.0.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.30.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.30.2 49152 > [TRACE] [UDP] Creating udp transport for 192.168.30.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.30.2 49152 > [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. > [TRACE] [UHD] Device hash: 2306081079422837585 > [INFO] [X300] X300 initialization sequence... > [DEBUG] [X300] Motherboard 0 has remote device ID: 1 > [DEBUG] [X300] Setting up basic communication... > [TRACE] [UDP] Creating udp transport for 192.168.30.2 49152 > [DEBUG] [X300] Using FPGA version: 39.1 git hash: 92c09f7 > [DEBUG] [X300] Loading values from EEPROM... > [TRACE] [UDP] Creating udp transport for 192.168.30.2 49152 > [TRACE] [UDP] Creating udp transport for 192.168.30.2 49158 > [DEBUG] [X300] Determining maximum frame size... > [INFO] [X300] Maximum frame size: 8000 bytes. > [DEBUG] [X300] Setting up RF frontend clocking... > [DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=8, Requested=0.000000, > Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns > [DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=4, Requested=0.000000, > Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns > [DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=5, Requested=0.000000, > Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns > [DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=0, Requested=0.000000, > Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns > [DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=2, Requested=0.000000, > Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns > [INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.929a > [INFO] [X300] Radio 1x clock: 200 MHz > [DEBUG] [X300] Motherboard 0 has local device IDs: > [DEBUG] [X300] * 2 > [TRACE] [UDP] Created UDP link to 192.168.30.2:49153 > [TRACE] [UDP] Local UDP socket endpoint: 192.168.30.1:46819 > [TRACE] [UDP] Target/actual recv sock buff size: 24912805/24912805 bytes > [TRACE] [UDP] Target/actual send sock buff size: 24912805/24912805 bytes > [DEBUG] [RFNOC::MGMT] Starting topology discovery from device[local]:2/sep:1 > [DEBUG] [RFNOC::MGMT] Discovered node device:1/xport:0 > [DEBUG] [RFNOC::MGMT] Initialized node device:1/xport:0 > [DEBUG] [RFNOC::MGMT] Discovered node device:1/xbar:0 > [DEBUG] [RFNOC::MGMT] Initialized node device:1/xbar:0 > [DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:0 > [DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:0 > [DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:1 > [DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:1 > [DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:2 > [DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:2 > [DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:3 > [DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:3 > [DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:4 > [DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:4 > [DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:5 > [DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:5 > [DEBUG] [RFNOC::MGMT] The following endpoints are reachable from > device[local]:2/sep:1 > [DEBUG] [RFNOC::MGMT] * 1:0 > [DEBUG] [RFNOC::MGMT] * 1:1 > [DEBUG] [RFNOC::MGMT] * 1:2 > [DEBUG] [RFNOC::MGMT] * 1:3 > [DEBUG] [RFNOC::MGMT] * 1:4 > [DEBUG] [RFNOC::MGMT] * 1:5 > [DEBUG] [RFNOC::LSM] Adding node device:1/xport:1 to topology graph outside > of discovery. > [DEBUG] [RFNOC::LSM] Adding transport adapter on xbar port 1 > [DEBUG] [RFNOC::GRAPH] Connecting the Host to Endpoint 1:0 through Adapter 0 > (0 = no preference)... > [DEBUG] [RFNOC::MGMT] Bound stream endpoint with Addr=(1,0) to EPID=2 > [DEBUG] [RFNOC] Started thread uhd_ctrl_ep0001 to process messages control > messages on EPID 1 > [DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2 > [DEBUG] [RFNOC] Created ctrlport endpoint for port 0 on EPID 1 > [DEBUG] [RFNOC::GRAPH] Connection to Endpoint 1:0 completed through Device 2. > Using EPIDs 1 -> 2. > [DEBUG] [RFNOC] Created ctrlport endpoint for port 2 on EPID 1 > [DEBUG] [0/DUC#0] Checking compat number for FPGA component `0/DUC#0': > Expecting 0.1, actual: 0.1. > [DEBUG] [0/DUC#0] Loading DUC with 3 halfbands and max CIC interpolation 255 > [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#0 (NOC ID=d0c00000) > [DEBUG] [RFNOC] Created ctrlport endpoint for port 3 on EPID 1 > [DEBUG] [0/DDC#0] Checking compat number for FPGA component `0/DDC#0': > Expecting 0.1, actual: 0.1. > [DEBUG] [0/DDC#0] Loading DDC with 3 halfbands and max CIC decimation 255 > [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#0 (NOC ID=ddc00000) > [DEBUG] [RFNOC] Created ctrlport endpoint for port 4 on EPID 1 > [DEBUG] [0/Radio#0] Checking compat number for FPGA component `0/Radio#0': > Expecting 0.1, actual: 0.1. > [DEBUG] [0/Radio#0] ADC capture delay self-cal done (Tap=16, Window=24, > TapDelay=78.125ps, Iter=1) > [TRACE] [UBX] UBX TX Gain: 0.000000 dB, Code: 0, IO Bits 0x0000 > [TRACE] [UBX] UBX TX: the requested frequency is 10.000000 MHz > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=4.000000, > fbdiv=42.000000 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=42, FRAC=0, MOD=4095, T=0, D=0, > RFdiv=2, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=2100.00, ACT=2100.00, VCO=4200.00, > PFD=50.00, BAND=0.05 > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=4.000000, > fbdiv=41.800000 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=41, FRAC=3276, MOD=4095, T=0, D=0, > RFdiv=2, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=2090.00, ACT=2090.00, VCO=4180.00, > PFD=50.00, BAND=0.05 > [TRACE] [UBX] UBX TX: the actual frequency is 10.000000 MHz > [TRACE] [UBX] UBX RX Gain: 0.000000 dB, Code: 0, IO Bits 0x0000 > [TRACE] [UBX] UBX RX: the requested frequency is 10.000000 MHz > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=4.000000, > fbdiv=47.600000 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=47, FRAC=2457, MOD=4095, T=0, D=0, > RFdiv=2, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=2380.00, ACT=2380.00, VCO=4760.00, > PFD=50.00, BAND=0.05 > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=4.000000, > fbdiv=47.400000 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=47, FRAC=1638, MOD=4095, T=0, D=0, > RFdiv=2, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=2370.00, ACT=2370.00, VCO=4740.00, > PFD=50.00, BAND=0.05 > [TRACE] [UBX] UBX RX: the actual frequency is 10.000000 MHz > [DEBUG] [0/Radio#0] Actual sample rate: 200 Msps. > [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#0 (NOC > ID=12ad1000) > [DEBUG] [RFNOC] Created ctrlport endpoint for port 5 on EPID 1 > [DEBUG] [0/DUC#1] Checking compat number for FPGA component `0/DUC#1': > Expecting 0.1, actual: 0.1. > [DEBUG] [0/DUC#1] Loading DUC with 3 halfbands and max CIC interpolation 255 > [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#1 (NOC ID=d0c00000) > [DEBUG] [RFNOC] Created ctrlport endpoint for port 6 on EPID 1 > [DEBUG] [0/DDC#1] Checking compat number for FPGA component `0/DDC#1': > Expecting 0.1, actual: 0.1. > [DEBUG] [0/DDC#1] Loading DDC with 3 halfbands and max CIC decimation 255 > [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#1 (NOC ID=ddc00000) > [DEBUG] [RFNOC] Created ctrlport endpoint for port 7 on EPID 1 > [DEBUG] [0/Radio#1] Checking compat number for FPGA component `0/Radio#1': > Expecting 0.1, actual: 0.1. > [DEBUG] [0/Radio#1] ADC capture delay self-cal done (Tap=20, Window=21, > TapDelay=78.125ps, Iter=1) > [TRACE] [UBX] UBX TX Gain: 0.000000 dB, Code: 0, IO Bits 0x0000 > [TRACE] [UBX] UBX TX: the requested frequency is 10.000000 MHz > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=4.000000, > fbdiv=42.000000 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=42, FRAC=0, MOD=4095, T=0, D=0, > RFdiv=2, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=2100.00, ACT=2100.00, VCO=4200.00, > PFD=50.00, BAND=0.05 > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=4.000000, > fbdiv=41.800000 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=41, FRAC=3276, MOD=4095, T=0, D=0, > RFdiv=2, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=2090.00, ACT=2090.00, VCO=4180.00, > PFD=50.00, BAND=0.05 > [TRACE] [UBX] UBX TX: the actual frequency is 10.000000 MHz > [TRACE] [UBX] UBX RX Gain: 0.000000 dB, Code: 0, IO Bits 0x0000 > [TRACE] [UBX] UBX RX: the requested frequency is 10.000000 MHz > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=4.000000, > fbdiv=47.600000 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=47, FRAC=2457, MOD=4095, T=0, D=0, > RFdiv=2, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=2380.00, ACT=2380.00, VCO=4760.00, > PFD=50.00, BAND=0.05 > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=4.000000, > fbdiv=47.400000 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=47, FRAC=1638, MOD=4095, T=0, D=0, > RFdiv=2, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=2370.00, ACT=2370.00, VCO=4740.00, > PFD=50.00, BAND=0.05 > [TRACE] [UBX] UBX RX: the actual frequency is 10.000000 MHz > [DEBUG] [0/Radio#1] Actual sample rate: 200 Msps. > [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#1 (NOC > ID=12ad1000) > [DEBUG] [RFNOC] Created ctrlport endpoint for port 8 on EPID 1 > [DEBUG] [0/Replay#0] Checking compat number for FPGA component `0/Replay#0': > Expecting 1.1, actual: 1.1. > [DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Replay#0 (NOC > ID=4e91a000) > [DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set. > [DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set. > [DEBUG] [0/DUC#1] Not setting frequency until sampling rate is set. > [DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set. > [DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set. > [DEBUG] [0/DUC#0] Not setting frequency until sampling rate is set. > [DEBUG] [0/Radio#0] Running ADC self-cal... > [DEBUG] [0/Radio#1] Running ADC self-cal... > Requesting sampling rate 200.0 Msps... > Using sampling rate: 200.0 Msps. > Requesting center frequency 1223.0 MHz... > [TRACE] [MULTI_USRP] Frequency Range 0.000MHz->6080.000MHz > Actual center frequency: 1223.0000032784735 MHz. > Requesting gain 20.0 dB... > [TRACE] [MULTI_USRP] Clipped RX frequency requested: 1223.000000MHz > Actual gain: 20.0 dB. > [TRACE] [MULTI_USRP] Target RF Freq: 1223.000000MHz > Selected 0 RX channels. > Generating RX streamer object... > [TRACE] [UBX] UBX RX: the requested frequency is 1223.000000 MHz > [TRACE] [MAX287X] Intermediates: ref=50000000.00, outdiv=8.000000, > fbdiv=24.460073 > [TRACE] [MAX287X] Tune: R=1, BS=1000, N=24, FRAC=1884, MOD=4095, T=0, D=0, > RFdiv=4, type=Fractional > [TRACE] [MAX287X] Frequencies (MHz): REQ=1223.00, ACT=1223.00, VCO=4892.00, > PFD=50.00, BAND=0.05 > [TRACE] [UBX] UBX RX: the actual frequency is 1223.003663 MHz > [TRACE] [MULTI_USRP] Target DSP Freq: 0.003663MHz > [TRACE] [UBX] UBX RX Gain: 20.000000 dB, Code: 40, IO Bits 0xa000 > [DEBUG] [CONVERT] get_converter: For converter ID: conversion ID > Input format: sc16_chdr > Num inputs: 1 > Output format: sc16 > Num outputs: 1 > Using best available prio: 0 > [TRACE] [UDP] Created UDP link to 192.168.30.2:49153 > [TRACE] [UDP] Local UDP socket endpoint: 192.168.30.1:36354 > [TRACE] [UDP] Target/actual recv sock buff size: 24912805/24912805 bytes > [TRACE] [UDP] Target/actual send sock buff size: 24912805/24912805 bytes > [DEBUG] [RFNOC::MGMT] Established a route from EPID=3 (SW) to EPID=2 > [DEBUG] [RFNOC::MGMT] Throttling stream endpoint to 100% (0x0) > [DEBUG] [RFNOC::MGMT] Initiated RX stream setup for EPID=2 > [DEBUG] [RFNOC::MGMT] Finished RX stream setup for EPID=2 > [DEBUG] [RFNOC::LSM] Remote stream is using different transport adapter > (device:1/xport:1) than local streamer object. Setting up remote route... > [DEBUG] [RFNOC::LSM] Adding virtual endpoint: device:2/virtual:3 (EPID: 3) > [DEBUG] [DEBUG] > /home/cjohnson/ettus_repo/uhd/host/lib/rfnoc/mgmt_portal.cpp:385 (virtual > void > uhd::rfnoc::mgmt::mgmt_portal_impl::setup_remote_route(uhd::rfnoc::chdr_ctrl_xport&, > const sep_id_t&, const sep_id_t&)) > [DEBUG] [RFNOC::MGMT] Programmed a route from EPID=1 to EPID=3 > [DEBUG] [RFNOC] Creating diverted RX stream with arguments: > dest_addr=192.168.30.30,dest_port=54321,stream_mode=raw_payload,adapter=sfp1,dest_mac_addr=3c:ec:ef:c2:43:47,enable_remote_stream=1,enable_fc=0 > [DEBUG] [X300::SFP1::TA_CTL] On transport adapter 1: Adding route from EPID 3 > to destination 192.168.30.30:54321 (MAC Address: 3c:ec:ef:c2:43:47), stream > mode RAW_PAYLOAD (1) > Starting stream... > Stream started. Press Ctrl-C to stop. > [DEBUG] [0/Radio#0] spp value 2044 exceeds MTU of 8000! Coercing to 1996 > > > ```
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