> > > One of the things that puzzles me is that 12.5Msps just isn't that high a > streaming rate, in fact it's totally supported over > a *1* GBit interface. > > At 12.5Msps, that buffer fills(drains) in about 2.5ms. There's plenty of > buffering on the host to buffer application scheduling > issues, so I don't know where these underruns would be coming from. > > I don't really know what the OS does in terms of "transmit" buffering (I'm slightly more confident on the OS behavior for the receive packets). I can say that avoiding "U" has always been harder for me than avoiding "O". My concern is that the OS is not doing much of any buffering on the Tx side (perhaps none) such that if things pause for the 2.5ms you mentioned, then "U" occurs.
But, one more comment about incorporating the DRAM fifo: I noticed that Ettus has a BIST image that uses this FIFO for the N310 (see here <https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/n3xx/n310_bist_image_core.yml>). So, this would be a great example to use for creating a custom image. Rob
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