On 28/03/2023 10:06, Rob Kossler via USRP-users wrote:
Hi Sorin,
Regarding the maximum LO offset you can use:
LO-offset-max = (master_clock_rate - sample_rate) / 2;
This equation ensures that your desired bandwidth (determined by
sample rate), will fit within the digital stream (at rate MCR) that
is supplied to the FPGA from the RF front end. So, with the B200
series, you need to set the master_clock_rate accordingly.
Rob
IN addition, on the B2xx, you need to set the analog bandwidth high
enough to accommodate that setting.
On Tue, Mar 28, 2023 at 9:54 AM <sor...@ayecka.com> wrote:
Thank you.
A. Let me understand. Can I make the lo_offset higher than
sampling rate/2 ?
B. I will try. About “But, also, consider LO offset in the TX path
as well.” I don’t want to use a tunable filter.
We did work with other Analog devices component. They are capable
of better performance than they show in your device.
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