Hello, I am trying to create a Vivado environment for the ettus 321, however, I am running into issues.
I navigated to uhd/fpga/usrp3/top/n3xx where there is a makefile which I assume creates the environment in Vivado. I run the makefile, but I end up with the error. It was successfully synthesized some of the netlists, but it fails on hb47_1to2, and I am not left with a vivado project I can open. I have pasted the error below. I am using Ubuntu 20.04, UHD 4.3.0, Vivado 2021.1 Thanks Joe ======================================================= BUILDER: Building IP hb47_1to2 ======================================================== BUILDER: Staging IP in build directory... BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2 BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2... BUILDER: Building IP... \[00:00:00\] Executing command: vivado -mode batch -source workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log hb47_1to2.log -nojournal \[00:00:05\] Current task: Initialization +++ Current Phase: Starting WARNING: \[IP_Flow 19-2162\] IP 'hb47_1to2' is locked: CRITICAL WARNING: \[filemgmt 20-1366\] Unable to reset target(s) for the following file is locked: workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci CRITICAL WARNING: \[filemgmt 20-1365\] Unable to generate target(s) for the following file is locked: workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci \[00:00:05\] Current task: Initialization +++ Current Phase: Finished \[00:00:05\] Executing Tcl: synth_design -top hb47_1to2 -part xc7z100ffg900-2 -mode out_of_context \[00:00:05\] Starting Synthesis Command WARNING: \[Vivado_Tcl 4-391\] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design. WARNING: \[IP_Flow 19-2162\] IP 'hb47_1to2' is locked: \[00:00:06\] Current task: Synthesis +++ Current Phase: Starting ERROR: \[Designutils 20-414\] HRTInvokeSpec : No Verilog or VHDL sources specified ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: \[Common 17-53\] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml' ERROR: \[Vivado 12-398\] No designs are open \[00:00:06\] Current task: Synthesis +++ Current Phase: Finished \[00:00:06\] Process terminated. Status: Failure ======================================================== Warnings: 3 Critical Warnings: 7 Errors: 8 BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2 make\[1\]: \*\*\* \[workarea/uhd/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc:19: IP_HB47_1TO2_TRGT\] Error 1 make\[1\]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx' make: \*\*\* \[Makefile:90: N3X0_IP\] Error 2
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