Seconding that.
Now, armchair network standardist here, but if I remember correctly, 2.5 Gb/s Ethernet is
a reduced-rate 10 GBase-T (so, pretty much IEEE802.3an-2006, with reduced clocks). I'm not
sure whether there's any other incompatibility between 802.3an-2006 and 802.3bz. But
honestly, the 10 GBase-T IP core is used in x300_sfpp_io_core.v, it's wrapped in the
ominously-named xge_max_wrapper.v, so go ahead and just drop-in replace it, if it can work
at the same 156.25 MHz symbol clock that. Don't know whether that works out-of-the-box,
but as long as you never remove the chinch / PCIe asic interface, you can always load a
working FPGA image via the JTAG interface, so stakes are quite low.
Cheers,
Marcus (the other!)
On 02.09.22 20:07, Marcus D. Leech wrote:
On 2022-09-02 12:48, Matthias Schraml wrote:
Hi all,
I’m currently wondering, if it is possible to use 2.5G ethernet with an USRP
X310.
Background:
I own a brand new small but powerful computer. The PCIe slot is occupied by a GPU and
there is no Thunderbolt port. So there is no chance for 10G ethernet.
However, the computer has a 2.5G ethernet port.
The Xilinx IP used for 1G ethernet in the USRPs also supports 2.5G. In theory, this
should be sufficient for 2x 30.72 MSps which would be a great improvement compared to
the 25 MSps over 1G ethernet.
Is it possible to modify the FPGA image to support 2.5G ethernet?
Has anybody already done this modification?
Kind regards
Matthias
The PHY implementation, as I recall, is fixed-rate. It's almost-certainly possible to
modify it to support it, but that wouldn't
be a configuration support by NI/Ettus.
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