Hi Kevin, I assume the xml you're referring to is the component description so that it can be recognized by Vivado IP integrator. In that case, you need to create an instance of the IP in Vivado, which will create an XCI file for it. You can then include that in the design similar to how other xci files are included in the build. Ettus has several IP components that get used this way (usually as part of a BD) which are located in fpga/usrp3/lib/vivado_ipi. This might serve as a reference.
If the code generated includes standard HDL (Verilog or VHDL) then you might also be able to include those as source in the design as another option. Wade On Tue, Aug 30, 2022 at 3:55 AM Kevin Williams <zs1...@gmail.com> wrote: > Hi Everyone, > > > > I’m a model-based firmware designer generating IP cores from Matlab and > Simulink. > > > > I see from one of the Ettus tutorials that it is easy to include a core > defined by an “xci” file, but not the “xml” descriptions from Simulink. > (This was the rfnoc_block_gain exercise.) > > > The folder in which those xml files live can be added as user repo's in > Vivado, and the core is recognised, but I have issues trying to use that IP > in the main design. > > > > Is this possible using the existing Ettus scripts? > > > Many thanks, Kevin > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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