Replace "upstream" with "downstream" below.

On Thu, Aug 18, 2022 at 1:28 PM Rob Kossler <rkoss...@nd.edu> wrote:

> Hi Adrian,
> As you indicated, the RFNoC blocks axi_ram_fifo and Relay both use the
> FPGA RAM.  axi_ram_fifo doesn't need any registers for control because it
> just accepts an AXI stream on the input and forwards that exact stream on
> the output.  The "control" is in the AXI tvalid/tready handshaking. Thus,
> if the upstream block is not ready, the FIFO starts filling up but does not
> empty until the upstream block is ready.  But, for the Replay block, this
> block stores the incoming stream to RAM until you later decide to play it
> out.  It can be used in the transmit path to load a waveform into RAM such
> that it can be played out to the Tx Radio without any help from the host
> PC.  Or, it can be used in the receive path to store receive samples as
> they arrive (up to the given RAM memory depth) and then later downloaded
> (played out) to the host PC in non-realtime.
>
> While I don't know your specific application, I wondered if the Replay
> block (or the axi_ram_fifo) can already implement your desired
> functionality such that a custom block is not needed.
> Rob
>
> On Thu, Aug 18, 2022 at 8:25 AM <adrian.cam...@integrasys-sa.com> wrote:
>
>> I am making a custom block which has to start storing data to be read
>> later, in other words store the data in a FIFO. I am interested in using
>> the RAM provided by the E320 so I want to take advantage of the
>> axi_ram_fifo code. However, I don't really understand the control of that
>> block, how can I control when to start writing data to memory and when to
>> start reading it? I have checked the registers in case it could be
>> controlled from there like the replay block that has two registers to start
>> reading and another one to do a restart but I haven't seen anything like
>> that.
>>
>> I hope you can help me. Thank you very much in advance
>>
>>
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>
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