Hi Rylee, Some blocks do use NIPC = 1, but those blocks need to use a faster clock for the internal processing. For example, on X310, the DDC and DUC use a separate CE clock that is connected to 214.286 MHz. The radio block uses radio_clk for this purpose. For the parts of the logic that use the 187.5 MHz clock, we use a 64-bit bus that holds 2 samples per cycle (NIPC = 2). The numbers vary somewhat between products and blocks, but that's the general idea.
Wade On Fri, Jul 1, 2022 at 8:55 AM Mattingly, Rylee <rmattin...@ou.edu> wrote: > Hello all, > > > > I am looking at the RFNoC FAQ page > <https://kb.ettus.com/RFNoC_Frequently_Asked_Questions> and it lists the > rfnoc_chdr clock as 187.5 MHz. Now this is plenty fast to pipe around > packets and sequential headers for the 184.32 MS/s sample rate but how does > this support the 200 MHz master clock/200MS/s sample rate? > > > > This seems like a NIPC > 1 would be needed, but my understanding is that > all blocks use NIPC = 1 by default. > > > > Thank you, > > > > Rylee Mattingly > > The University of Oklahoma > > Graduate Research Assistant > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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