On 2022-05-26 10:31, luca.vi...@argotecgroup.com wrote:
Hi all!
I am starting to look through some of the FPGA code of the USRP X300
in order to understand which is the DDC chain configuration in the
default image.
I have understood that in the DDC chain there is 1 CIC filter + 3
Halfband filters. Since I want to characterize the DDC chain I have
the following questions:
1.
How are they used? I suppose that the halfband filters are used
based on the decimation factor we need (max. 1024)
2.
Which is the order of the CIC filter?
3.
How many taps each halfband filters have? Which are the taps?
Thank you in advance,
Luca
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Some of that is configured on the *HOST* side, in
host/lib/usrp/cores/rx_dsp_core_3000.cpp In fact a lot of the DSP
setup and configuration is
"orchestrated" on the host side, with the host setting registers on
the FPGA. The FPGA doesn't really "know" how to configure the DDC chain
itself--that
is determined by the host library.
The filter coefficients and order of the CIC filter is determined in the
FPGA code *somewhere*, but I'm not sure where. It has literally been
nearly a decade since I
had all of that in my head.
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