Hi all, Long time no see! I am currently on a final stretches of completing a masters project for my wireless embedded systems program that involves a USRP X310 with RFNoC 4.0 and GNURadio that implements a Hierarchical Modulation design using nested 4QAM / QPSK (final constellation "appears" like 16QAM but has embedded high priority and low priority layers that can adapt based on SNR).
I am currently attempting to integrate the Xilinx Convolutional Encoder v9.0 IP block into the template rfnoc_block_conv.v design that was created using rfnocmodtool and modeled after the Ettus FFT example. With a bit of work I was able to get the .xci file loaded by Vivado when the make target is executed for the testbench, and the testbench appears to build without much modification. When executing 'make rfnoc_block_conv_tb' it appears to fully execute the build process to the end, but I receive a fatal "Did not receive CTRL_STS_OKAY status" message in the process which I attribute to either something not being configured in the testbench file or something not being configured right in my verilog module file. I've attempted to summarize where I'm stuck and need help on in the below three summary points / questions: 1) I have configured the convolutional encoder with rate 1/2 and punctured (effective rate 2/3), which I assume will require me modifying the "axi_wrapper" so that the output to input ratios are set properly - are there additional examples that I can follow for this? I've seen the axi_wrapper migration note but as I'm still a novice at Verilog and System Verilog additional examples would be helpful. :) 2) I would like to modify my testbench so that I send 10 bytes (80 bits) of data, and read out the 15 bytes (120 bits) that get spit out and verify that the encoded bytes coming out of the core match ground truth data I would generate using MATLAB. Do we have any additional testbench examples or additional documentation that show sending 1 or more bytes of data through an IP core? The IP core's *s_axis_data_tdata* and *m_axis_data_tdata *are 8-bit while most of the examples show sending 32 bits. Aside from setting the assignments to [7:0] are there any other adjustments that need to be made in any of the signal declarations and/or block definition wires earlier in the file? I've provided the IP core documentation for reference just in case: https://docs.xilinx.com/v/u/en-US/pg026_convolution I've also included the module and testbench files as well as the xsim log. Thanks in advance! -Jeff
rfnoc_block_conv.v
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rfnoc_block_conv_tb.sv
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xsim.log
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