Hi, I apparently loaded a bad bistream onto my e320 (in case) and now it seems bricked. I am trying to use the jtag programmer on vivado 2019.1 -> digilent onboard jtag programmer -> reprogram the fpga. Unfortunately the stm32 turns off the zynq as quickly as it comes up, is there a way to override this behavior? I can't connect long enough to program the fpga...
[0.000402 Inits done] [0.034887 SW 0x01] Enclosure version ... using alternative thermal parameters Console is enabled; type HELP for help. > [0.045631 power state 4 = G3->S5, in 0x0000] [0.045802 power state 1 = S5, in 0x0000] [0.045943 power state 5 = S5->S3, in 0x0000] [0.046128 event set 0x00002000] [0.046246 hostcmd init 0x2000] [0.060204 power state 2 = S3, in 0x0002] [0.074684 power state 6 = S3->S0, in 0x01fe] [1.074914 AP didn't come up, shutdown] [1.075083 power state 7 = S0->S3, in 0x01fe] [1.091168 Watchdog timeout, warm reset the AP] [1.091308 event set 0x00100000] [1.108303 power state 2 = S3, in 0x0002] [1.108489 power state 8 = S3->S5, in 0x0002] [1.108706 power state 1 = S5, in 0x0000] [1.108857 power state 9 = S5->G3, in 0x0000] [1.109018 power state 0 = G3, in 0x0000] [1.319702 power state 4 = G3->S5, in 0x0000] [1.319895 power state 1 = S5, in 0x0000] [1.320047 power state 5 = S5->S3, in 0x0000] [1.334169 power state 2 = S3, in 0x0002] [1.348719 power state 6 = S3->S0, in 0x01fe] [2.348960 AP didn't come up, shutdown] [2.349132 power state 7 = S0->S3, in 0x01fe] [2.365217 Watchdog timeout, warm reset the AP] [2.382343 power state 2 = S3, in 0x0002] [2.382531 power state 8 = S3->S5, in 0x0002] [2.382750 power state 1 = S5, in 0x0000] [2.382904 power state 9 = S5->G3, in 0x0000] [2.383068 power state 0 = G3, in 0x0000] Thanks for any suggestions- Mike
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
